Re: Verilog-AMS Committee Meeting Minutes - Mar 1st 2007

From: Marq Kole <marq.kole_at_.....>
Date: Thu Mar 15 2007 - 09:20:18 PDT

Geoffrey,

It was a question from a language point-of-view rather than an application point-of-view. I think indeed have string output variables has little merit, but if we decide so, we should make that explicit. I'm in favour of having as little as possible implementation dependent language constructs. Explicitly disallowing string output variables would actually have my vote.

Cheers,
Marq


Marq Kole
Competence Leader Robust Design

Research
NXP Semiconductors
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"Geoffrey.Coram" <Geoffrey.Coram@analog.com> Sent by: geoffrey.coram@analog.com 15-03-2007 16:16

To Marq Kole <marq.kole@nxp.com> cc verilog-ams <verilog-ams@eda-stds.org> Subject Re: Verilog-AMS Committee Meeting Minutes - Mar 1st 2007 Classification

What in the world is a string output variable, and how
would you plot it??

-Geoffrey


Marq Kole wrote:
>
> All,
>
> > * Martin to talk to Geoffrey about reworking Chapter 3 to support
> > strings variables
>
> Just an idea, but should string variables also be supported as output variables, i.e. should section 3.1.1 be extended with string output variables as well?
>


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