Kevin Cameron <kevin@sonicsinc.com> wrote on
18-04-2007 01:57:59:
<snip>
> The switches in a wired-or would all be switch
branches (potential 0, or
> open). Multiple potential 0 contributions in parallel are not a problem
> physically, but if the voltage is calculated dynamically you can't
> statically analyze the case.
<snip>
> If putting modules with simple switches and ideal batteries in parallel
> works OK then I won't have a problem.
But this is not allowed in the current Verilog-AMS
standard either if you were to implement it using parallel instances of
switches. The ability to handle multiple analog blocks is not going to
change this behavior because that is not its aim.
If you can convince the Verilog-AMS committee to support
this for parallel switch instances then it will automatically work for
multiple analog blocks, but it is independent of the multiple analog blocks
proposal! And vice versa, if there are reasonable arguments not to allow
this for parallel switch instances, then the same will apply to multiple
analog blocks.
Marq
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Received on Wed Apr 18 02:48:43 2007