RE: array parameters overrides

Marq,

 

See Mantis 1209.

 

I agree it needs to be an error.

 

Note that in IEEE 1800 syntax, the list of array values needs to be
enclosed in '{}, with an apostrophe before the curly bracket.

 

Also, 1800 8.13 says,

 

An assignment-like context is as follows:

...

- For a parameter with an explicit type declaration:

- A parameter value assignment in a module, interface, program, or class

- A parameter value override in the instantiation of a module,
interface, or program

 

and 5.7 says,

Assigning to a fixed-size unpacked array requires that the source and
the target both be arrays with the same

number of unpacked dimensions, the length of each dimension be the same,
and each element be of an

equivalent type.

 

Regards,

Shalom

 

________________________________

From: owner-verilog-ams@server.eda.org
[mailto:owner-verilog-ams@server.eda.org] On Behalf Of Marq Kole
Sent: Tuesday, April 17, 2007 5:45 PM
To: verilog-ams
Subject: RE: array parameters overrides

 


Shalom, 

Thanks; from what I read in the IEEE 1800-2005 standard (although module
instance parameters are not mentioned in section 19.11, but task and
function parameters are) array parameters have to match in size,
according to section 12.4. That seems to indicate that in Verilog-AMS
LRM 2.3 we should make this an error as well. 

Cheers, 
Marq 


Marq Kole
Domain Leader Robust Design

Research
NXP Semiconductors









"Bresticker, Shalom" <shalom.bresticker@intel.com> 

17-04-2007 15:26 

To

"Marq Kole" <marq.kole@nxp.com>
"verilog-ams" <verilog-ams@server.eda-stds.org> 

cc

 

Subject

RE: array parameters overrides 

Classification

 

 

 

 




1364-2005 does not have array parameters, only 1800-2005. 
  
Shalom 
  

 

________________________________


From: owner-verilog-ams@server.eda.org
[mailto:owner-verilog-ams@server.eda.org] On Behalf Of Marq Kole
Sent: Tuesday, April 17, 2007 4:24 PM
To: verilog-ams
Subject: array parameters overrides 
  

All, 

In the Verilog-AMS 2.2 LRM there is nothing specified about overriding
array parameters; also in IEEE 1364-2005 nothing is mentioned on this
item. 

Considerthe following Verilog-A code: 

module map(a, b); 
 inout a, b; 
 electrical a, b; 
 parameter real ap[0:3] = { 0.0, 0.707, 1.0, 1.414 }; 

 genvar i; 

 analog 
   for (i = 0; i <= 3; i = i + 1) 
     $write("ap[%d] = %g\n", i, ap[i]); 

endmodule // map

module test_map(a, b); 
 inout a, b; 
 electrical a, b; 

 // overriding array length == 1 
 map #(.ap({ 1.2 })) X1 (a, b); 
 // overriding array length == 5 
 map #(.ap({ 3.1415, -1.01, 2.2u, 1e-9, 10.0 })) X2 (a, b); 

endmodule // test_map 

What would happen when the compiler/interpreter encounters the
instantiations X1 and X2? I could not find any reference in the standard
documents. To prevent ambiguity in the various simulators I suggest that
the elaboration is defined, for instance in section 7.2 in the
Verilog-AMS LRM and/or in section 12.2.2 in IEEE 1364-2005. 

Personally, I would expect an error to occur for both instantiations,
essentially signalling a mismatch in length between the overriding and
overridden arrays. 

Cheers, 
Marq 


Marq Kole
Domain Leader Robust Design

Research
NXP Semiconductors

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