Overview of multiple analog blocks impact

All,

From a review of LRM 2.2 and the sections updated and reviewed so far for 
LRM 2.3, I find that most of the text needed for the support of multiple 
analog blocks needs to be added to section 6 (Analog Behavior). In 
particular, I suggest to start from the latest version of merged_beh.pdf 
from the public documents section of the Verilog-AMS committee.

As a suggestion for the sections and kinds of changes, here is an 
overview. I've also tried to note whether most issues are known and a 
solution has been proposed.

6.1 Analog Procedural Block
--> remove text stating the limitation to a single analog block
    [no issues]

6.1.1 Concurrent Analog Blocks [NEW]
--> describe multiple (concurrent) analog blocks
    [no issues]

...

6.2.1 Sequential Blocks
--> add the concatenate sequential block syntax to Syntax 6-2
    [use concatenate syntax as agreed in the committee telecon of April 
12, 2007]
--> allow branch declaration at the top of an analog sequential block
    [branch declarations are module level declarations in LRM 2.2, but 
need to be allowed in analog sequential blocks as well, both named and 
unnamed. However, it needs to be restricted to the top-level analog 
sequential blocks. Need to assess the implications for the Verilog-AMS 2.3 
syntax.] 

6.2.3 Concatenated Analog Blocks [NEW]
--> describe the concatenation of named and unnamed analog blocks
    [use concatenate syntax as agreed in the committee telecon of April 
12, 2007]

...

6.3.1.3 Value Retention
--> add a description for value retention in case of multiple concurrent 
analog blocks
    [refer to section 6.1.1 to describe value retention for unnamed 
branches in case of multiple concurrent analog blocks. Similarly explain 
use of analog block level named branches in cases where the unnamed 
module-level branches cannot be used.]

6.3.1.4 Switch Branches
--> add a limitation to allow switch branches only in a single analog 
block
    [disallow switch branches distributed over multiple concurrent analog 
blocks, as agreed in the committee telecon of April 12, 2007]

6.4.1 Concurrent Assignment
--> describe the limitations to variable assignments in case of multiple 
concurrent analog blocks
    [open issue: should the concurrent analog blocks be evaluated 
atomically as suggested as an optional requirement in the Multiple Analog 
Blocks V4 document section 3.1?]
    [open issue: add a requirement for the run-time detection of race 
conditions in case of assignment to the same variable in multiple 
concurrent analog blocks?]

6.4.1.1 Concurrent Variable Access [NEW]
--> related to the concurrent variable assignment there is also the issue 
of variable access in case of multiple concurrent analog blocks
    [open issue: no decision yet on how to handle reliable access to a 
variable that has been assigned a value in another concurrent analog 
block]

With the multiple analog blocks  defined mainly in section 6, there are 
few isolated places in the rest of the LRM that need to be updated.

7.1 Modules
--> add text describing the support of multiple analog blocks.
    [no issues]

Comments are welcome.

Cheers,
Marq


Marq Kole
Domain Leader Robust Design

Research
NXP Semiconductors

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