Re: disallow distributed switch branches

From: Kevin Cameron <kevin_at_.....>
Date: Wed Apr 18 2007 - 13:52:38 PDT

Geoffrey.Coram wrote:

Kevin Cameron wrote:
  

I see absolutely no reason for disallowing these cases. As previously
discussed, the behavior of an analog statements should not change if
they are moved from separate modules into the same module
    

Much as you'd like this to be true, we discussed this in last
week's call and decided it doesn't work when contributing to
potentials.  Since named branches are declared at module scope,
if you contribute to the potential of a branch in two analog
blocks, the values add; if you put the analog contrib statements
into separate modules, the potentials are in parallel (and you'll
get an error from many simulators).

-Geoffrey
  

If

The behavior of an analog blocks should not change if they are moved from separate modules into the same module.

holds, then

If you contribute to the potential of a branch in two analog blocks, the values add; if you put the analog contrib statements into separate modules, the potentials are in parallel.

is untrue.

Since there is no prior specification for the behavior for multiple analog blocks in the same module I propose that the contributions are in parallel for consistent behavior. Where the branch is declared is immaterial.

You would only get that problem if you were automatically concatenating analog blocks - but we are not doing that so there is no issue, and no need to disallow multiple switch branches.

The behavior for a concatenated block should be the same as it is if the block was declared as one block.

We also know that simulators can handle parallel potential contributions. A goal of Verilog-AMS is to be able to reliably describe hardware, not the lowest common denominator of what existing simulators are capable of.

Kev.









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