Re: update multiple analog blocks document V4

IMO the document is getting too long and confusing now, also I think 
some of it is based on incorrect assumptions.

There seems to be an implicit assumption somewhere that analog block 
semantics applied at a module level rather than at the block level. I 
don't think there is a pre-existing statement anywhere that potential 
contributions in one block should add with another's if they are in the 
same module - and I see no reason for doing that other than if the 
blocks are explicitly concatenated.

The race condition section makes assumptions about how simulators work 
which are incorrect, the only race condition is in the copy-out phase of 
solving the matrix. If anyone who has actually implemented a simulator 
has a different opinion I'll be happy to hear it.

Kev.

Marq Kole wrote:
>
> All,
>
> An update of the Multiple Analog Blocks document has been posted to 
> the public documents area of the Verilog-AMS standardization committee.
>
> http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/Multiple_Analog_Blocks_v4.pdf 
>
>
> Cheers,
> Marq
>
>
> Marq Kole
> Domain Leader Robust Design
>
> Research
> NXP Semiconductors
> Tel: +31 40 27 49051, Fax: +31 40 27 46276, Mobile: +31 6 387 48 389
> High Tech Campus HTC-37.4.037, 5656 AE Eindhoven, The Netherlands
> marq.kole@nxp.com, www.nxp.com
>
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