Re: disallow distributed switch branches

Marq Kole wrote:
>
> owner-verilog-ams@server.eda.org wrote on 18-04-2007 22:52:38:
>
> <snip>
>
> > If
> > /The behavior of an analog blocks should not change if they are 
> moved from separate modules into the same module.// /
> > holds, then
> > I/f you contribute to the potential of a branch in two analog 
> blocks, the values add; if you put the analog contrib statements into 
> separate modules, the potentials are in parallel.// /
> > is untrue.
>
> Then one should conclude that the above proposition (The behavior ... 
> same module) is false.
 From a programmers perspective it is extremely bad to have the same 
piece of code do different thing in different contexts - a guaranteed 
source of bugs.
> The reason that it is false is that the contribution statements 
> involving unnamed branches refer to separate unnamed branches in the 
> case of separate modules, but refer to the same module-level branches 
> in the case of multiple concurrent analog blocks. The conclusion is 
> that the behavior of analog blocks does change if they are moved from 
> separate modules into the same module BUT IN SEPARATE CONCURRENT 
> ANALOG BLOCKS.
A branch declaration is a shorthand for accessing a unique (global) node 
pair. For simulation a design is usually considered flattened, i.e. the 
local branch information is generally ignored and only the absolute node 
pair considered.
> The fact that we propose separate approaches to concurrent and 
> concatenated analog blocks is a dead giveaway of this distinction.
How?  It's just syntactic sugar, there's no reason a sequence of 
concatenated blocks should behave differently than if you wrote it as 
one block - as above it would be bad if the behavior was different.

> > Since there is no prior specification for the behavior for multiple
> > analog blocks in the same module I propose that the contributions
> > are in parallel for consistent behavior. Where the branch is
> > declared is immaterial.
>
> Well, the committee members available in the telecon of April 12 
> propose that the contributions act as described in the minutes of that 
> call. We agreed that the declaration of the branch IS important as 
> suggested and made plausible by Ken in his posting from January 31st.
> (see http://www.eda-stds.org/verilog-ams/hm/1922.html)
I think Ken is making an assumption based on how Spectre works rather 
than what's in the LRM.

As far as I'm concerned all contributions from analog processes (blocks) 
to a given branch/node-pair should be considered as being in parallel. 
Only internal to an analog block do potential contributions sum.

> > You would only get that problem if you were automatically
> > concatenating analog blocks - but we are not doing that so there is
> > no issue, and no need to disallow multiple switch branches.
>
> The problem is in the combination of switch branches, concurrency and 
> value retention, but we've been through these moves before as in the 
> email thread started on January 26th.
> (see http://www.eda-stds.org/verilog-ams/hm/1893.html)
Yes, and I'm saying you have the wrong solution. A bunch of switch 
branches in parallel is perfectly legitimate hardware, I should be able 
to describe it.

Kev.
>
> Marq
>
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