Re: disallow distributed switch branches

Kevin Cameron wrote:
> (see http://www.eda-stds.org/verilog-ams/hm/1922.html) 
..
> I think Ken is making an assumption based on how Spectre works rather 
> than what's in the LRM.
Sorry Ken - misread the old posting.
*
*What I think Ken was asking for is the summing behavior you get within 
a block, but spanning multiple blocks, which is what you get with 
concatenated blocks - so still no reason for making the in-module 
behavior different.


Concatenation is a blunt instrument and you may run into the problem 
that if a large sprawling concatenate happens to contribute potential to 
more than one branch, then they will all sum - which might have 
undesirable consequences.

If you want to be explicit about the behavior than you probably need to 
actually mark the branch with an attribute e.g.

  branch summing (a,b) emf;

- instruct compiler that (potential) contributions for this branch sum 
from all independent analog blocks using it. That would give Ken what he 
wanted without using concatenation, which might work better in a 
multirate model.

Likewise if you have something in a concatenated blocks you need to do 
the opposite with, something like:

  branch parallel (a,b) emf;

- which could give you either an elaboration or run-time error if you 
try to contribute a potential in more than one block of a concatenate.

If you don't like "summing" and "parallel" being keywords you could use 
"+" and "||".

Kev.



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