Re: disallow distributed switch branches

Geoffrey.Coram wrote:
> Kevin -
> No, I'm not confusing the issues.
>
> This code:
>
>    module A ...
>        electrical a,b;
>        analog  begin
>                V(a,b) <+ 5;
>                V(a,b) <+ 6;
>        end
>    endmodule
>
> works presently in AMS, and gives 11.  If you split them into
> separate modules, then it fails because they're in parallel.
>
> I think that your first module, with
>        analog  V(a,b) <+ 5;
>        analog  V(a,b) <+ 6;
> is "more like" my module above, hence, I think that the
> behavior of multiple analog blocks should be "more like"
> multiple contribs in one block (rather than multiple
> instances).
>   
That doesn't really make sense, on that argument you would sum all 
potential contributions from all modules.

Contributions from analog blocks in different modules are in parallel 
for potential and flow - thats the way it has always been. I'm just 
asking for that behavior to apply consistently.

--

I'll restate my requirement:

    1. Multiple analog blocks connected to the same branches/nodes 
should behave the same regardless of whether they are in the same module 
or different modules.

Ken's request is for:

    2. A mechanism to sum potential contributions across multiple analog 
blocks rather than the default of them being in parallel.

Marq's requirement is:

    3. A mechanism to coalesce multiple analog blocks into one in a 
module for ease-of-use.


Having the default behavior be that the potential contributions in a 
module are parallel for multiple analog blocks answers 1. Using an 
explicit concatenate answers 2 & 3. I don't see a conflict.

Kev.

> -Geoffrey
>
>
>
>
> Kevin Cameron wrote:
>   
>> You are confusing the issues. The problem is if you have
>>
>>    module A ...
>>        electrical a,b;
>>        analog  V(a,b) <+ 5;
>>        analog  V(a,b) <+ 6;
>>    endmodule
>>
>> Which would work under Marq's proposed rules giving V(a,b) == 11, but if you split it into submodules:
>>
>>    module A ...
>>        electrical a,b;
>>        B;
>>        C;
>>   endmodule
>>
>>   module B..
>>        analog  V(A.a,A.b) <+ 5;
>>   endmodule
>>   module C
>>        analog  V(A.a,A.b) <+ 6;
>>   endmodule
>>
>> That fails because the contributions are now considered as being in parallel.
>>     


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