Re: disallow distributed switch branches

From: Kevin Cameron <kevin_at_.....>
Date: Fri Apr 20 2007 - 10:34:05 PDT

I think you are missing my point: regardless of what the LRM currently says, as a hardware engineer (conversant in Verilog, but new to AMS)  why would I expect the two versions of the same circuit to behave differently?

Kev.

Geoffrey.Coram wrote:

Kevin Cameron wrote:
  

You are confusing the issues. The problem is if you have

   module A ...
       electrical a,b;
       analog  V(a,b) <+ 5;
       analog  V(a,b) <+ 6;
   endmodule

Which would work under Marq's proposed rules giving V(a,b) == 11, but if you split it into submodules:

   module A ...
       electrical a,b;
       B;
       C;
  endmodule

  module B..
       analog  V(A.a,A.b) <+ 5;
  endmodule
  module C
       analog  V(A.a,A.b) <+ 6;
  endmodule

That fails because the contributions are now considered as being in parallel.
    

I think, actually, that this fails now because
a) module A has a branch (a,b) that has nothing
assigned to it, so by 5.1.6, "If a value is not
assigned to a branch, the branch flow is set 
to zero (0)."
b) the contributions in the analog blocks of B and C
would make (a,b) into a switch branch
c) 5.3.1.3 says it is illegal to contribute to
an external switch branch from within an analog block

If you re-wrote module A as:

   module A ...
       electrical a,b;
       B;
       C;
       analog V(a,b) <+ 0;
  endmodule

then I believe that the last sentence of Section 7.5
(for source branches, contributions can be made to
the output signal) means that the contributions in
modules B and C add to the 0, and you should get 11.

-Geoffrey
  

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