Date & Time: 26 April 2007 Call-In Details: USA Toll Free Number: 877-346-8823 USA Toll Number: +1-203-320-0407 (for intl) Participant Passcode: 602538 The call times are: 06:30 am US Pacific 08:30 am US Central 09:30 am US Eastern 15:30 pm Eindhoven 19:00 pm Noida 23:00 pm Adelaide Agenda for the call: - Review of the revised Verilog-AMS examples (Marq) [It was noted in last week's minutes that the issues raised by Paul Floyd on atan2 and mod will be updated on the draft chapter 4 document as the issues have been acknowledged] Future discussion points for LRM 2.3 (hopefully in the order specified below for upcoming meetings): - $table_model proposal on chapter 10 (Patrick, Tiburon) - Modified idt() analog operator proposal (Ken Kundert) - Proposal on ACMI and changes related to support for multiple power domains (Kevin Cameron); Cadence is also planning to submit a proposal on this problem which looks at the backward compatibility issues (Martin O'leary) - $table_model proposal on chapter 10 (Patrick, Tiburon) - LRM 2.3 edits of chapter 8 (I think this is Dave/FSL, I need to check) & chapter 9 (Junwei Hou, Cadence) - Section 11 on compiler directives (Graham Helwig, ASTC) - Annexures (No assigned owners yet for this apart Annex A by Graham and Annex E by Marq Kole) cheers, Sri -- Srikanth Chandrasekaran Design Technology (Tools Development) Freescale Semiconductor Inc. Ph: +91-120-439 7021 F: x5199 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Apr 25 07:56:48 2007
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