RE: disallow distributed switch branches

Marq,
 
I agree, I misused the word "assignment" when I was referring to
the "==" operator in VHDL-AMS.  I understand that VHDL-AMS does
not assign the value obtained from the right side to the left
side of that operator, but instead it "solves" the equation.
 
However, I would argue with you on saying that the "==" operator
is very similar to "<+" in Verilog-AMS, because to me it seems to
be a completely different thing to say that the right and left
side of the equation are equal ("=="), or that the left side of
the equation will increase by the amount on the right side of
the equation ("<+").
 
I don't think I was saying that these two syntaxes can't be
converted from one to another but I think it is not an easy task,
because instead of looking at the code line by line, you have to
trace the entire model to find all contributions to the same
branch before you can write the corresponding equation in VHDL-AMS.
This takes a little more work whether a person does it or a machine.
I think our friends at Lynguent could comment on that better than me.
 
I don't dispute that the incremental construction of equations in
Verilog-AMS makes code extension easy.  Each language has its own
beauties, and after a while the question of who likes what feature
will become a matter personal taste which will also depend a lot
on what the language is used for.  I could say that the "==" 
operator has a nice feature that I haven't seen in Verilog-AMS,
which is that you can have an expression on the left side also,
not just a single variable.  The equation solver will sort it out
for you, you don't have to worry about rearranging the equation
algebraically.  This can be a very useful feature too, because in
certain cases it is not possible to collect the like variables
on one side of the operator...
 
Arpad
===================================================================
 


________________________________

From: owner-verilog-ams@server.eda.org [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Marq Kole
Sent: Sunday, April 22, 2007 12:40 PM
To: verilog-ams
Subject: RE: disallow distributed switch branches



Arpad, 

Actually, the "==" operator in VHDL-AMS is very similar to the contribution operator in Verilog-AMS and it is not an assignment -- it is a simultaneous statement. An assignment is essentially an asymmetric statement in that there is one side "producing" a value and the other side "consuming a value". The contribution statement in Verilog-AMS and the simultaneous statement in VHDL-AMS both create a new equation, specifically a differential-algebraic equation (DAE). These statements are much more symmetric than simple assignments. Effectively analog models in a Verilog-AMS description or a VHDL-AMS description contain such statements that together form a system of equations that needs to be solved for a simulation to progress.

On the other hand, there are differences between VHDL-AMS and Verilog-AMS in the way that the equations are constructed. The main difference is that VHDL-AMS requires the equation to be complete, while Verilog-AMS allows the equation to be contructed in an incremental fashion. This gives Verilog-AMS the ability to modularize or extend the code quite simply, while in VHDL-AMS it is easier to understand the whole equation system. In my perception it is possible to provide (simple) rewrite rules that would allow a piece of (analog) VHDL-AMS code to be rewritten in Verilog-A and vice versa. 

Cheers, 
Marq 


Marq Kole
Domain Leader Robust Design

Research
NXP Semiconductors

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