RE: disallow distributed switch branches

That may be so (I have to think about it a little more),
but last time I tried it wasn't implemented in my tool... 

Arpad
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-----Original Message-----
From: owner-verilog-ams@server.eda.org [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Geoffrey.Coram
Sent: Wednesday, April 25, 2007 9:18 AM
Cc: verilog-ams
Subject: Re: disallow distributed switch branches

"Muranyi, Arpad" wrote:
> 
>  ...    I could say that the "=="
> operator has a nice feature that I haven't seen in Verilog-AMS,
> which is that you can have an expression on the left side also,
> not just a single variable.  The equation solver will sort it out
> for you, you don't have to worry about rearranging the equation
> algebraically.  This can be a very useful feature too, because in
> certain cases it is not possible to collect the like variables
> on one side of the operator...

At first glance, I think "indirect assignments" in Verilog-AMS
give you that ability.

-Geoffrey

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