"Muranyi, Arpad" wrote: > > ... I could say that the "==" > operator has a nice feature that I haven't seen in Verilog-AMS, > which is that you can have an expression on the left side also, > not just a single variable. The equation solver will sort it out > for you, you don't have to worry about rearranging the equation > algebraically. This can be a very useful feature too, because in > certain cases it is not possible to collect the like variables > on one side of the operator... At first glance, I think "indirect assignments" in Verilog-AMS give you that ability. -Geoffrey -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Apr 25 09:19:38 2007
This archive was generated by hypermail 2.1.8 : Wed Apr 25 2007 - 09:19:41 PDT