Verilog-AMS LRM Committee Meeting - 17 May

From: Sri Chandra <sri.chandra_at_.....>
Date: Wed May 16 2007 - 05:58:30 PDT
Date & Time: 17 May 2007

Call-In Details:
    USA Toll Free: 877-346-8823
    USA Toll: +1-203-320-0407
    Passcode: 602538

Call times:
06:30am US Pacific
08:30am US Central
09:30am US Eastern
15:30pm Eindhoven
19:00pm Noida
23:00pm Adelaide


Agenda:
    - idt() analog operator proposal (Ken Kundert)
    - $table_model proposal (Patrick O'Halloran)

I am hoping Ken would be able to attend the meeting tomorrow to go over 
the idt() proposal discussions, followed by the $table_model discussion 
from Tiburon.

Outstanding Proposals:
    - Proposal on ACMI and changes related to support for multiple power
domains. Kevin has already submitted a proposal on this and Cadence is
also planning to submit a proposal for this issue which also discusses
backward compatibility while addressing the open issue.
    - LRM2.3 edits for Chapter 8, Chapter 9
    - LRM2.3 edits for Annex chapters

cheers,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199

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Received on Wed May 16 05:58:58 2007

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