Encryption from Verilog to Verilog-AMS?

 
A lot of industry discussion has been devoted lately to reconciling the
Accellera and IEEE versions of several HDLs, both at the digital and
mixed signal level.  

One feature of particular interest is encryption.  Both the IEEE 1364
Verilog specification Annex H and Accellera draft version of IEEE 1076
VHDL describe a macro syntax to support code encryption.  When will the
digital Verilog encryption syntax "migrate" into the AMS specification?


IC vendors are concerned about IP protection, and the macro approach
seems to be the most general-purpose way of accommodating IP protection
while taking tool variations and national policies into account.  As
IBIS now supports code written in either AMS language, IC vendors
interested in distributing IBIS+AMS models for signal integrity
simulations need a solution.

Thanks in advance.

- Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum

Disclaimer: this communication does not necessarily represent policy,
commitments or preferences for Intel Corp. or the IBIS Open Forum

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