Hello All, Before I start to make changes to the chapter 11 (directives), I have summarized the major changes to chapter that I can see occurring. Please review. Since 1364-2005 has introduced the `begin_keyword and `end_keyword directives, how should the predefined __VAMS__ and __VAMS_ COMPACT_MODELING__ macros should be handled differently in Verilog-AMS LRM 2.3? Should the `begin_keyword and `end_keyword directives be extended to include Verilog-AMS specific versions or subsets? - section 11 (Introduction) - Change references from 1364-1995 to 1364-2005 - Expand list of AMS directives to include directives from the 1364-2005 section. Refer directives unaffected by AMS to 1364-2005, all others refer to section numbers - section 11.1: `default_discipline - No change - section 11.2 `default_transition - No change - section 11.3 `define and `undef - Collapse section down to a reference to 1364-2005, except for the paragraph referring to __VAMS__? - section 11.4 `ifdef, `else and '`endif - Remove section and refer to 1364-2005 in the introduction - section 11.5 `include - Remove section and refer to 1364-2005 in the introduction - section 11.6 `resetall - Remove section and refer 1364-2005 in introduction - section 11.7 Predefined Macros - update4 references to 1364-1995 and version fo the Verilog-AMS LRM - `celldefine and `endcelldefine - No AMS specific behavior is present and therefore no section needs to be added - `default_nettype - No AMS specific behavior is present and therefore no section needs to be added - `line - No AMS specific behavior is present and therefore no section needs to be added - `timescale - No AMS specific behavior is present and therefore no section needs to be added - `unconnected_drive and `nounconnected_drive - No AMS specific behavior is present and therefore no section needs to be added - `pragma - No AMS specific behavior is present and therefore no section needs to be added - `begin_keywords and `end_keywords - extend the 1364-2005 version specifier to include specific versions of the Verilog-AMS LRM or subsets of keywords (i.e. analog or compact modeling)? - ` default_analog - is this multiple analog block directive going to be added into the language? Regards Graham -- ========================================================== Graham Helwig AMS Verification Australian Semiconductor Technology Company (ASTC) Pty Ltd Location: 76 Waymouth St, Adelaide, SA, 5000, Australia Phone +61-8-82312782 Moblie: +61-4-03395909 Email: graham.helwig@astc-design.com Web: www.astc-design.com ========================================================== -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu May 17 22:28:51 2007
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