Verilog-AMS Committee Meeting Agenda - 28 June 2007

Hi all,

Date & Time: 28 June 2007

Call-In Details:
    USA Toll Free: 877-346-8823
    USA Toll: +1-203-320-0407
    Passcode: 602538

Call times:
06:30am US Pacific
08:30am US Central
09:30am US Eastern
15:30pm Eindhoven
19:00pm Noida
23:00pm Adelaide

Agenda:
   - $table_model proposal update (if there is an update sent by Patrick 
on this)
   - Annex E updates

Just putting a plan for next few calls, we can look at the following:
   - idt proposal (chapter 4 - Dave)
   - compiler directives (chapter 11 - Graham)
   - Chapter 8 (mixed signal - dave)
   - Chapter 9 (scheduling semantics - cadence)

in the above order.

Martin - any update on the proposal from Cadence on handling multiple 
power supplies and related ACMI issues?

cheers.
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
Ph: +91-120-439 7021 F: x5199

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.