Re: update of Annex E

And how to include sections.. 
I would suggest that we revise the header paragraph to add the mention that ALL device/source models and their parameters (corners, randomization etc)  can be supported as verilog-A compact models, and reference the appropriate chapter or annex where that use model is defined. 

Jonathan
  
Jonathan David
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----- Original Message ----
From: Geoffrey.Coram <Geoffrey.Coram@analog.com>
To: Marq Kole <marq.kole@nxp.com>
Cc: verilog-ams <verilog-ams@eda-stds.org>
Sent: Wednesday, June 27, 2007 4:27:28 AM
Subject: Re: update of Annex E

Marq -
The document is there now:
http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/merged_spice.pdf

I tend to agree about removing diode, etc.  I wonder, though,
if the Annex should say something about referring to Spice
elements, whether they are .model cards or .subckts.  It
might be as little as "Simulator vendors shall document
the methods and restrictions of accessing SPICE .model cards
from within a Verilog-AMS netlist."

-Geoffrey



Marq Kole wrote:
> 
> All,
> 
> I've just asked Geoffrey Coram to upload a new version of the Annex E (SPICE compatibility) document to the Verilog-AMS website for review tomorrow. It should be there under the name merged_spice.pdf.
> 
> Most of the Mantis items mentioned for Annex E have been processed in this document, except for those relating to Tables E.1 and E.2. My proposal is to integrate the tables into a single table that also describes exactly the behavior of each primitive and hence the influence of each parameter. Also, the items requiring a model (diode, bjt, mosfet, mesfet, and jfet) should be removed from the table as they do not appear in Verilog-AMS netlists as a reference to SPICE primitives. So there is no need to pollute the namespace of Verilog-AMS with these names that are not used anyway.
> 
> Would that be acceptable?
> 
> Cheers,
> Marq

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