Date: Wed Jun 27 2007 - 23:57:04 PDT
Jonathan, I'm not convinced this is necessary - this goes beyond just supporting the models/subcircuits/primitives which is necessary for using legacy SPICE netlists in a Verilog-AMS top-level. By performing the section includes in the SPICE part of the description the correct (process/global) parameters would be available to the SPICE models/subcircuits/primitives which can be included in the LRM 2.2 way in Verilog-AMS modules. Why do you think access to sections and parameter sets is needed? Cheers, Marq To "Geoffrey.Coram" <Geoffrey.Coram@analog.com> Jonathan David Marq Kole <marq.kole@nxp.com> <jb_david@yahoo.com> cc verilog-ams 27-06-2007 23:39 <verilog-ams@eda-stds.org> Subject Re: update of Annex E Classification And how to include sections.. I would suggest that we revise the header paragraph to add the mention that ALL device/source models and their parameters (corners, randomization etc) can be supported as verilog-A compact models, and reference the appropriate chapter or annex where that use model is defined. Jonathan Jonathan David j.david@ieee.org jb_david@yahoo.com http://ieee-jbdavid.blogspot.com Mobile 408 390 2425 Work: jbdavid@scintera.com http://www.scintera.com 408 636-2618 ----- Original Message ---- From: Geoffrey.Coram <Geoffrey.Coram@analog.com> To: Marq Kole <marq.kole@nxp.com> Cc: verilog-ams <verilog-ams@eda-stds.org> Sent: Wednesday, June 27, 2007 4:27:28 AM Subject: Re: update of Annex E Marq - The document is there now: http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/merged_spice.pdf I tend to agree about removing diode, etc. I wonder, though, if the Annex should say something about referring to Spice elements, whether they are .model cards or .subckts. It might be as little as "Simulator vendors shall document the methods and restrictions of accessing SPICE .model cards from within a Verilog-AMS netlist." -Geoffrey Marq Kole wrote: > > All, > > I've just asked Geoffrey Coram to upload a new version of the Annex E (SPICE compatibility) document to the Verilog-AMS website for review tomorrow. It should be there under the name merged_spice.pdf. > > Most of the Mantis items mentioned for Annex E have been processed in this document, except for those relating to Tables E.1 and E.2. My proposal is to integrate the tables into a single table that also describes exactly the behavior of each primitive and hence the influence of each parameter. Also, the items requiring a model (diode, bjt, mosfet, mesfet, and jfet) should be removed from the table as they do not appear in Verilog-AMS netlists as a reference to SPICE primitives. So there is no need to pollute the namespace of Verilog-AMS with these names that are not used anyway. > > Would that be acceptable? > > Cheers, > Marq -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
