Minutes LRM Committee Meeting - 19th July 2007

Attendees:
   David Miller - Freescale
   Sri Chandra - Freescale
   Geoffrey Coram - Analog Devices
   Boris Troyanovsky - Tiburon
   Patrick O'Halloran - Tiburon
   Cadence

# Reviewed Chapter 8 - Mixed Signal.
Issues to resolve are:
   * Change back all references to Verilog-AMS to Verilog-AMS HDL to remain
     consistent with other chapters.

   * Section 8.3.2 - check font of keywords in the example.
   * Should we refer to the discipline 'logic' in the examples? Better to refer
     to the new discipline to avoid clashes with SV. David to check with Martin
     what that is (\logic)
   * example should be 'else if (dnet === 1'bx)'
   * For the note at the end of the section that refers to 1354-2005, mention
     the actual chapter that discusses the case equality / inequality operators.

   * Section 8.3.4 - Restore the syntax box that was used to list the type of
     events in Verilog-AMS.

   * Section 8.3.6.2 - Semicolon ';' in example

   * Section 8.3.7 - David to check constant analog UDF's are allowed in
     declaration statements and whether that is refered to as a continuous
     context (since it is outside an analog begin .. end block).

   * Section 8.4.1 - try and attach the figure caption to the figure.

   * Kevin Cameron also sent through some suggested changes via email that David
     will incorporate into the rework.

# Discussed $simprobe system function. The main purpose of this function is to
probe dynamic quantities of a sibling spice instance. This function is not OOMR
as we are looking for an instance that is parent of the parents children.
So to avoid confusion and to not have too many ways to do hierarchical
reference, $simprobe will be restricted to just get a value from an instance in
the parents children. It will not allow you to continue to search up the
hierarchy or to obtain a value from an instance using a full hierarchical
reference.
i.e.
module bb;
   real x;
   analog x = $simprobe("m1","i");
endmodule

This will look for an instance called 'm1' in the instantiation list of the
parent of bb, once that instance is found, the value for 'i' will be probed.

David to provide a simple SPICE example of how this function will be used to
measure a value during simulation. Will also update Chapter 10 with this
change.

# Discussed $freq. The intention of this function was not to change the op
values of the circuit with each new frequency. This function is used mainly in
debugging, $debug, $fwrite, etc. However it was decided to not add this
function in for LRM 2.3.
It was also decided to modify noise_table() where if the first argument is a
string literal or string parameter, then it represents the name of a file that
contains freq/pwr pairs. Dave to update Chapter 4 with this change, and to also
list the format of the file. Should be similar to table model, # lines and
blank lines are ignored, other lines should contain 1 frequency / pwr pair
value. This modification will not break any existing models using
noise_table().

Next meeting scheduled for 26th July.

Cheers...
Dave
-- 
=====================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
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