[Fwd: Re: Proposal for two additional environment parameter functions]

Just noticed that Ken sent this owner-verilog-ams instead of verilog-ams...

-------- Original Message --------
Subject: Re: Proposal for two additional environment parameter functions
Date: Fri, 13 Jul 2007 15:18:28 -0700
From: Ken Kundert
To: Jonathan David, owner-verilog-ams@eda.org

Jonathan,
     Verilog-A/MS is a modeling language. What you want is a measurement
language.

With a modeling language, you are modeling the device under test (DUT).
The simulator is then free to analyze that model in any way it sees fit.
  With AC & Noise analysis, it linearizes the model. Once it extracts the
linearized model, it no longer needs to evaluate the model. This is why
implementing $freq represents a big change for the implementations. The
request to add $freq is a request to tailor the language to a particular
SPICE analysis. We have done these things before, but very sparingly.
Adding $freq was specifically considered and rejected because it
represents a big and very complex change, and it is problematic in many
ways.

In contrast, a measurement language operates on the data produced by the
simulator. Thus, it very naturally can analyze the output of an AC
analysis and extract 3dB bandwidth and the like.

The concept of modeling and measurement language have been mixed up with
Verilog because Verilog simulators perform only a simple transient
analysis, and thus do not need to cope with small-signal analyses, RF
analyses, etc.

-Ken

Jonathan David wrote:
> My reason to want it is similar.. 
> I'm using Verilog-A to capture simulation results (in a standard way no matter which simulator, or where in the heirarchy the design element being tested is) , which, without $freq, is useless for small-signal results. I also don't want to modify the simulation - but I do want to be able to capture things like 3db BW.. and gain at "X"hz  - and min and max frequency simulated.. 
> 
>  
> Jonathan David

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