My recollection is that at one of the meetings this year, we discussed this issue and agreed to remove this phrase so I agree with Ken on this. I guess the note was overlooked. Thanks, --Martin -----Original Message----- From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Ken Kundert Sent: Monday, October 01, 2007 5:21 PM To: verilog-AMS LRM Committee Subject: Section 7.5: Hierarchical names On the top of page 148 in the section on hierarchical names, the LRM 2.2 says: From within an analog block, it is possible to use hierarchical name referencing to access signals on an external branch, but not external analog variables or parameters. There is no reason why parameter need to be included in this restriction, and it would be nice to be able to have global access to parameters and localparameters. Can we remove the phrase "or parameters"? -Ken -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon, 1 Oct 2007 18:48:03 -0700
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