error in 7.3.1

Martin,
    I actually was looking at the published LRM rather than the latest
version, so it might have been fixed already.

However, I found a new problem. This time in section the example of
section 7.3.1 (page 138 of published LRM).

In this example a module is defined called semicoCMOS, and then a
several hierarchical references are made to it. But this is wrong. You
cannot reference a module definition. You must reference an instance of
a module. So, this example needs to be modified in two ways. First, the
semicoCMOS module must be instantiated. Second, the references should be
modified so they refer to the instance rather than the module definition.

-Ken

Martin O'Leary wrote:
> My recollection is that at one of the meetings this year, we discussed
> this issue and agreed to remove this phrase so I agree with Ken on this.
> I guess the note was overlooked.
> Thanks,
> --Martin
> 
> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
> Behalf Of Ken Kundert
> Sent: Monday, October 01, 2007 5:21 PM
> To: verilog-AMS LRM Committee
> Subject: Section 7.5: Hierarchical names
> 
> On the top of page 148 in the section on hierarchical names, the LRM 2.2
> says:
> 
> From within an analog block, it is possible to use hierarchical name
> referencing to access signals on an external branch, but not external
> analog variables or parameters.
> 
> There is no reason why parameter need to be included in this
> restriction, and it would be nice to be able to have global access to
> parameters and localparameters. Can we remove the phrase "or
> parameters"?
> 
> -Ken
> 
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