RE: error in 7.3.1

You can reference a module name in an upward hierarchical reference.

See the following example from Gordon Vreugdenhil.

"The basic idea is that there are two "names" -- the name of the module 
scope and the name of the instance.  Here is an example: 

   module top; 
      child c1(); 
   endmodule 

   module child; 
      initial child.x = 1; 
      initial top.c1.x = 1; 
       // but top.child.x is not Ok 

      reg x; 
   endmodule  "

Shalom

> -----Original Message-----
> From: owner-verilog-ams@server.eda.org 
> [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Ken Kundert
> Sent: Tuesday, October 02, 2007 4:28 AM
> To: verilog-AMS LRM Committee
> Subject: error in 7.3.1
> 
> Martin,
>     I actually was looking at the published LRM rather than 
> the latest version, so it might have been fixed already.
> 
> However, I found a new problem. This time in section the 
> example of section 7.3.1 (page 138 of published LRM).
> 
> In this example a module is defined called semicoCMOS, and 
> then a several hierarchical references are made to it. But 
> this is wrong. You cannot reference a module definition. You 
> must reference an instance of a module. So, this example 
> needs to be modified in two ways. First, the semicoCMOS 
> module must be instantiated. Second, the references should be 
> modified so they refer to the instance rather than the module 
> definition.
> 
> -Ken
> 
> Martin O'Leary wrote:
> > My recollection is that at one of the meetings this year, 
> we discussed 
> > this issue and agreed to remove this phrase so I agree with 
> Ken on this.
> > I guess the note was overlooked.
> > Thanks,
> > --Martin
> > 
> > -----Original Message-----
> > From: owner-verilog-ams@eda.org 
> [mailto:owner-verilog-ams@eda.org] On 
> > Behalf Of Ken Kundert
> > Sent: Monday, October 01, 2007 5:21 PM
> > To: verilog-AMS LRM Committee
> > Subject: Section 7.5: Hierarchical names
> > 
> > On the top of page 148 in the section on hierarchical 
> names, the LRM 
> > 2.2
> > says:
> > 
> > From within an analog block, it is possible to use 
> hierarchical name 
> > referencing to access signals on an external branch, but 
> not external 
> > analog variables or parameters.
> > 
> > There is no reason why parameter need to be included in this 
> > restriction, and it would be nice to be able to have global 
> access to 
> > parameters and localparameters. Can we remove the phrase "or 
> > parameters"?
> > 
> > -Ken
> > 
> > --
> > This message has been scanned for viruses and dangerous content by 
> > MailScanner, and is believed to be clean.
> > 
> > 
> 
> --
> This message has been scanned for viruses and dangerous 
> content by MailScanner, and is believed to be clean.
> 
> 
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.