Date: Thu Oct 11 2007 - 02:23:51 PDT
Sri, Unfortunately, I did not have the time to finish Annex C in time for the review. I should be able to provide a version in time for next weeks meeting, though. I am sorry not to have lived up to my earlier promises, but all kinds of other issues at NXP have been taking 110% of my time, leaving too little time for Verilog-AMS standardization. I hope you can understand my prioritizations. CHeers, Marq To Verilog-AMS LRM Committee <verilog-ams@server.eda.org> Sri Chandra cc <sri.chandra@freesca le.com> Subject Agenda for Verilog-AMS committee Sent by: meeting - 11 Oct 2007 owner-verilog-ams@se Classification rver.eda.org 10-10-2007 20:49 Date & Time: 11 Oct 2007 Call-In Details: USA Toll Free: 877-346-8823 USA Toll: +1-203-320-0407 Passcode: 602538 Call times: 06:30am US Pacific 08:30am US Central 09:30am US Eastern 15:30pm Eindhoven 19:00pm Noida 23:00pm Adelaide Agenda: - Annex C review Marq: I am not sure whether this chapter is ready for review yet. Can you respond to the reflector confirming whether we will have the review of Annex C please. Regards. Sri -- Srikanth Chandrasekaran Design Technology (Tools Development) Freescale Semiconductor Inc. T:+91-120-439 5000 p:x3824 f: x5199 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
