Re: Agenda for Verilog-AMS committee meeting - 11 Oct 2007

Marq,

No worries. You have done lot of work during the the LRM2.3 development 
& standardization process, so there is no need to apologize :) I can 
understand other commitments that you would have to focus on.

We will try to target the meeting next week and see how it goes. In the 
mean time, I will start working on merging chapters 5 & 6 as we decided 
earlier and try and having it ready in a fortnights time.

We will cancel today's meeting and take this up along with corrections 
that were suggested in Chapter 9 during last week's meeting. Hopefully 
it shouldn't take more than one sitting to have a go at both chapter 9 
correction and Annex C.

Regards,
Sri

Marq Kole wrote:
> Sri,
> 
> Unfortunately, I did not have the time to finish Annex C in time for the 
> review. I should be able to provide a version in time for next weeks 
> meeting, though.
> 
> I am sorry not to have lived up to my earlier promises, but all kinds of 
> other issues at NXP have been taking 110% of my time, leaving too little 
> time for Verilog-AMS standardization. I hope you can understand my 
> prioritizations.
> 
> CHeers,
> Marq
> 
> 
> Inactive hide details for Sri Chandra <sri.chandra@freescale.com>Sri 
> Chandra <sri.chandra@freescale.com>
> 
> 
>       *Sri Chandra <sri.chandra@freescale.com>*
> 
>       Sent by:
>       owner-verilog-ams@server.eda.org
> 
>       10-10-2007 20:49
> 
> 	
> 
> To
> 	
> Verilog-AMS LRM Committee <verilog-ams@server.eda.org>
> 
> cc
> 	
> 
> Subject
> 	
> Agenda for Verilog-AMS committee meeting - 11 Oct 2007
> 
> Classification
> 	
> 
> 	
> 
> 
> Date & Time: 11 Oct 2007
> 
> Call-In Details:
>    USA Toll Free: 877-346-8823
>    USA Toll: +1-203-320-0407
>    Passcode: 602538
> 
> Call times:
> 06:30am US Pacific
> 08:30am US Central
> 09:30am US Eastern
> 15:30pm Eindhoven
> 19:00pm Noida
> 23:00pm Adelaide
> 
> Agenda:
>   - Annex C review
> 
> Marq: I am not sure whether this chapter is ready for review yet. Can
> you respond to the reflector confirming whether we will have the review
> of Annex C please.
> 
> Regards.
> Sri
> -- 
> Srikanth Chandrasekaran
> Design Technology (Tools Development)
> Freescale Semiconductor Inc.
> T:+91-120-439 5000 p:x3824 f: x5199
> 
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-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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