string definition

All,

In the currently proposed updates of chapters 2 (Lexical Conventions) and 3
(Data Types) there is a considerable overlap related to strings (section
2.6 and section 3.2), in particular concerning the use of the label "string
variable".

The whole text of section 2.6 has been taken over verbatim from the digital
verilog definition, which is currenly present in IEEE 1364-2005 as section
3.6. As the definition of string variables in this section is based purely
on the mapping on register variables which are only available in the
digital context, I would suggest to remove this section entirely (with the
exception of subsection 2.6.3 that deals with special characters). As I
recall for this standard we want to refer to IEEE-1364-2005 whereever
possible, instead of copying the related sections.

Instead, I suggest to write a new section based on the contents of section
3.6 from the IEEE 1800-2005 SystemVerilog standard which presents only
string literals (disregarding for the packing of strings which we do not
want to support). This is more appropriate for the chapter title (which
considers lexical conventions, not data types) and can describe string
literals as usable for both digital string constants and variables,
SystemVerilog string constants and variables and Verilog-AMS string
parameters.

If considered appropriate, I can make a proposal for the new text of
section 2.6 of the current Verilog-AMS proposed update.

The contents of section 3.2 do not need to be changed, although a reference
to IEEE 1364-2005 string variable definition may need to be added - it is
only implied by the current text.

Best regards,
Marq

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