Re: minutes Verilog-AMS committee meeting November 29, 2007

Hi all,

As per Marq's email moving forward any changes to the documentation we 
will channel it through Stu. There are two options:

* Either send the approved changes to the LRM text (with exact 
references) to Stu who can make the changes to the documentation (or)
* Please acquire an edited latest frame version from Stu if you do feel 
that its easier for you to make the changes to the documentation.

Post draft2 release all changes will be recorded on Mantis and its 
easier to send to Stu any changes that are required.

Also, thanks to Marq for chairing the AMS committee over the last month. 
Much appreciate it.

Regards,
Sri

Marq Kole wrote:
> Verilog-AMS Standardization Conference Call
> 
> November 29, 2007
> 
> Attending:
> - David Miller, Freescale
> - Sri Chandra, Freescale
> - Martin O'Leary, Cadence
> - Stu Sutherland, Sutherland HDL
> - Marq Kole, NXP
> 
> Analog Inital Block:
> 
>     * Martin sent around an analog initial block proposal among the
>       active participants of the Verilog-AMS standardization committee
>       before sending it out on the public pages or the reflector. Dave,
>       Geoffrey, and Marq provided feedback on this proposal and Martin
>       will update it accordingly before publishing it on the public web
>       pages.
>     * Still some discussion was brought up on whether the analog initial
>       blockwas necessary - its benefit over a regular initial_step event
>       is that it is guaranteed to be executed at most one time during
>       each analysis task.
>     * An analog final block was decided to be postponed till the next
>       version of the standard when it merges with SystemVerilog. It
>       turns out that the final block was introduced with SV and is not
>       present in 1364-2005. Marq will make a Mantis entry for an analog
>       final block.
>     * Another item was Dave's comment on using OOMRs in an analog
>       initial block. As the analog initial block is executed when the
>       elaboration is finished, a variable OOMR should be allowed - there
>       were questions on whether an analog variable OOMR was possible
>       because of lacking derivative information. Sri will make a
>       subsection to section 6.6 (Hierarchical names) to describe exactly
>       what is allowed with hierarchical references and hierarchical names.
> 
> 
> 
> Status of the Draft Document:
> 
>     * For the syntax in Annex A. Graham will provide a document to Stu
>       that highlights the changes with respect to the Annex A currently
>       present in Draft A. This allows Stu to get the current draft up to
>       date without having to undo the edits that he had performed on
>       Annex A over the past weeks.
>     * Any editing items shall from now on be handled through Mantis
>       Issues so Stu can handle the edits accordingly. If larger edits
>       are required one can also request the frame source from Stu,
>       perform the edits in Framemaker and send the edited document back
>       to Stu. In the end, Stu will need to have full control over the
>       editing process of the Verilog-AMS 2.3 standard to be able to
>       perform his duties as Technical Editor.
>     * According to Stu IEEE labels successive drafts by number rather
>       than by letter - we will adhere to this custom and call the next
>       draft of the standard document Draft 2.
>     * The original plan for Stu was to have the first draft ready by
>       December 1, but as it took 10 days to get all the various frame
>       sources to him from the start of November, there is a slight
>       delay. He now expects to have a first draft of the Verilog-AMS 2.3
>       standard (Draft 2) ready by the end of next week - December 7.
> 
> 
> 
> Next meeting
> 
>     * Sri will take over as chair again from now on.
>     * The next Verilog-AMS Standardization conference call will be on
>       December 6, 2007.
> 
> 
> 
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-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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