Re: minutes Verilog-AMS committee meeting November 29, 2007

Sorry I keep missing the calls.

Marq Kole wrote:
>     * Still some discussion was brought up on whether the analog initial
>       blockwas necessary - its benefit over a regular initial_step event
>       is that it is guaranteed to be executed at most one time during
>       each analysis task.

The proposal I saw from Martin says you will get one execution
per step of a dc sweep.  This is because some people (eg, compact
model writers) want to put temperature-adjustments in a special
block so they "know" it gets done once for transient, but if
you're sweeping temperature, it needs to be done more than once.

On the other hand, if you're sweeping a voltage source external
to the module, then the analog initial block does *not* need to
be re-executed.  Are we *requiring* the simulator to re-exec
the block?

Although Martin's e-mail said the a.i.b. was for "initialization
such as reading data from a file," that's not in the LRM, and we
can't prevent compact-modelers from using the block for other
purposes.


>     * Another item was Dave's comment on using OOMRs in an analog
>       initial block. As the analog initial block is executed when the
>       elaboration is finished, a variable OOMR should be allowed - there
>       were questions on whether an analog variable OOMR was possible
>       because of lacking derivative information. Sri will make a
>       subsection to section 6.6 (Hierarchical names) to describe exactly
>       what is allowed with hierarchical references and hierarchical names.

As to the variable OOMR: if it's in the analog initial block,
then the OOMR should not be allowed to reference a variable
that depends on a voltage, just as statements in the analog
initial block can't have access functions in them, so the
derivative information should always be zero.

Dave's concerns about race conditions should be expressed
in the LRM as a caution.

-Geoffrey

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