Re: IEEE std on Verilog AMS

Marq,

I was under the impression that a goal of the committee (from its 
inception) was to create a unified AMS HDL, and since most Verilog work 
is now at the IEEE, AMS was to be transferred to the IEEE P1800 effort 
as soon as possible. Are you saying that is not the goal, and as an end 
user you (and NXP) are happy to see multiple versions of Verilog and a 
fractured analog/digital design community?

The original Verilog-AMS Design Objectives Document 
<http://eda.org/verilog-ams/htmlpages/dod.html> is well out-of-date now, 
it might be a good idea to create a new one so that we all know what the 
current goals are.

Kev.

Marq Kole wrote:
>
> Hi Joginder,
>
> Standardization efforts are currently performed within the Accellera 
> standardization organization, although there is a long term intent to 
> have Verilog-AMS become an IEEE standard, we're currently not working 
> on that. We do however try to conform as much as possible to IEEE 
> standards with the upcoming 2.3 release of the standard. This will 
> make the transition from an Accellera standard into an IEEE standard 
> simpler. The fully approved 2.3 standard can reasonably be expected 
> somewhere in the middle of next year. On the public documents site of 
> the Verilog-AMS standardization website (www.eda-stds.org/verilog-ams) 
> draft versions of the various chapters and an initial draft of the 
> standard can be found.
>
> Verilog-AMS is very well supported in the commercial EDA offerings 
> from many companies: the big EDA companies all have their mixed-signal 
> simulation environment supporting Verilog-AMS, mostly adhering to the 
> 2.2 standard. There are also offerings from smaller companies 
> specializing in mixed signal simulation solutions. Next to that the 
> analog subset known as Verilog-A is supported in nearly all analog, 
> SPICE-like simulators on the market.
>
> I hope this answers your questions, but feel free to ask if anything 
> is unclear.
>
> Best regards,
> Marq
>
>
> Inactive hide details for "Joginder Singh" 
> <joginder.singh@gmail.com>"Joginder Singh" <joginder.singh@gmail.com>
>
>
>       *"Joginder Singh" <joginder.singh@gmail.com>*
>
>       Sent by:
>       owner-verilog-ams@server.eda.org
>
>       07-12-2007 13:55
>
> 	
>
> To
> 	
> "verilog-AMS LRM Committee" <verilog-ams@server.eda.org>
>
> cc
> 	
> "Joginder Singh" <joginder.singh@gmail.com>
>
> Subject
> 	
> IEEE std on Verilog AMS
>
> Classification
> 	
>
> 	
>
>
> Hi All,
>
> I understand there is significant effort going on for statndardization
> Verilog AMS. And it is in use in design projects. I am curious to know
> as to how soon will we have an IEEE standard
> finalized/approved/published. Could someone from standardization
> committee please throw some light on this?
>
> Other things I would appreciate knowing are how good is the support by
> existing simulators and its popularity among analog/ams designers.
> Well, that is a wider question but it always has made me curious.
> -- 
> Regards,
> Joginder.
>
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