Re: IEEE std on Verilog AMS

From: Marq Kole <marq.kole_at_.....>
Date: Fri Dec 07 2007 - 07:56:25 PST
Hi Joginder,

Standardization efforts are currently performed within the Accellera
standardization organization, although there is a long term intent to have
Verilog-AMS become an IEEE standard, we're currently not working  on that.
We do however try to conform as much as possible to IEEE standards with the
upcoming 2.3 release of the standard. This will make the transition from an
Accellera standard into an IEEE standard simpler. The fully approved 2.3
standard can reasonably be expected somewhere in the middle of next year.
On the public documents site of the Verilog-AMS standardization website
(www.eda-stds.org/verilog-ams) draft versions of the various chapters and
an initial draft of the standard can be found.

Verilog-AMS is very well supported in the commercial EDA offerings from
many companies: the big EDA companies all have their mixed-signal
simulation environment supporting Verilog-AMS, mostly adhering to the 2.2
standard. There are also offerings from smaller companies specializing in
mixed signal simulation solutions. Next to that the analog subset known as
Verilog-A is supported in nearly all analog, SPICE-like simulators on the
market.

I hope this answers your questions, but feel free to ask if anything is
unclear.

Best regards,
Marq




                                                                       
                                                                       
                                                                       
                                                                        To
                                       "verilog-AMS LRM Committee"     
                                       <verilog-ams@server.eda.org>    
     "Joginder Singh"                                                   cc
     <joginder.singh@gmai              "Joginder Singh"                
     l.com>                            <joginder.singh@gmail.com>      
                                                                   Subject
     Sent by:                          IEEE std on Verilog AMS         
     owner-verilog-ams@se                                   Classification
     rver.eda.org                                                      
                                                                       
     07-12-2007 13:55                                                  
                                                                       
                                                                       
                                                                       
                                                                       




Hi All,

I understand there is significant effort going on for statndardization
Verilog AMS. And it is in use in design projects. I am curious to know
as to how soon will we have an IEEE standard
finalized/approved/published. Could someone from standardization
committee please throw some light on this?

Other things I would appreciate knowing are how good is the support by
existing simulators and its popularity among analog/ams designers.
Well, that is a wider question but it always has made me curious.
--
Regards,
Joginder.

--
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.





graycol.gif pic28811.gif ecblank.gif
Received on Fri Dec 7 08:00:43 2007

This archive was generated by hypermail 2.1.8 : Fri Dec 07 2007 - 08:00:56 PST