Minutes of Verilog-AMS committee conference call - 24 Jan 2007

Date: 24th Jan 2008 (9:00pm Pacific)

Attendees:
* Patrick O'Halloran - Tiburon
* Martin O'Leary, Cadence
* Marq Kole, NXP
* Dave Miller, Freescale
* Marek Mierzwinski, Tiburon
* Jonathan David, Scintera
* Graham Helwig, ASTC
* David Sharrit, Tiburon

The following agenda items were addressed:
   - Section 6.6.1 - Hierarchical references
   - Analog Initial Block proposal
   - Chapter 7, Mixed-Signal

Hierarchical references
------------------------

Discussion on the reflector already seemed to indicate that the OOMR access
   of analog variables should probably not be allowed. The use case in
   favor of allowing OOMR access would be to be able to access analog
   variables values from a test bench. The simplest "work around" is to
   assign the analog variable value to a digital variable value for which
   OOMR access is allowed. This does not work in two cases: the analog-only
   (Verilog-A) case, and the case in which legacy code with analog
   variables is used. Both cases were considered to be not sufficiently
   strong to warrant OOMR access to analog variables. Therefore, the
   section 6.6.1 in Sri's proposal of January 16 can be used with the
   exception of the 4th bulletpoint that allows OOMR access of analog
   variables. (Probably the 4th bulletpoint should be rewritten to
   specifically make it an error.)

The current text proposal of Sri with the abovementioned amendments can be
   introduced in Draft3 (proposal MK, not discussed in the meeting: as
   section 6.7.1, making it a subsection of the seciont 6.7 on hierarchical
   names.)

A proposal was to create an example with the section that would show the
   abovementioned work-around for analog variable OOMR access through a
   local digital variable.

Analog Initial Block
--------------------

The latest document from Martin on the analog initial block was discussed.
   This was made available on the public documents section of the
   Verilog-AMS committee's website (see email message from David Miller
   dated Jan 24).

The proposal was accepted with one additional item: the analog initial
   block cannot access any digital as the digital has not initialized at
   that point so is not available. Martin will add an extra sentence
   describing this limitation to the proposal, post a final update of the
   impact document describing the analog initial block and send a version
   of that to Stu Sutherland for incorporation into Draft 3.

Review of Draft 2
-------------------

Review notes: (page number references are to the actual document page
numbers and not the pdf page numbers)

* Chapter 7, Mixed-Signal
   - (pg 158) in table 7-1, the "bit" entry in the rightmost column at the
   bottom row should be replaced by "scalar, vector" as that seems to be
   the correct 1364-2005 name. The wire declaration in the 2nd column at
   the bottom row may not be appropriate as that has not been resolved to a
   particular type. It would be nice if one of the digital gurus could shed
   some light on this.
   - (pg 159) the example is missing a declaration of the variable var,
   i.e.:
      real var;
   just below the "electrical anet" declaration.


Next meeting: 31 Jan, 2008:
   - Continue from Chapter 7, section 7.4 and onwards


Cheers,
Marq
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