Re: [Fwd: Minutes of Verilog-AMS meeting - 31 Jan 2008]

Indeed.  However, the syntax shows that the argument to $random
may be omitted.  V-AMS explicitly notes that, and says that
the simulator will pick a seed -- and, presumably, creates an
integer variable to hold the value.

Thus, one could also allow parameters or integral constants
and have the simulator create a variable to hold the value
and handle the updates, and just initialize it to the value
of the constant expression.

-Geoffrey


Bresticker, Shalom wrote:
> 1800 says, "The seed argument shall be an integral variable".
> 
> Shalom 
> 
>> I don't see any mention in the minutes of the $random and 
>> $rdist functions being reviewed.  In particular, the whole 
>> business of the type_string argument is poorly explained in 
>> the current LRM.
>> (What is the default behavior, if no type_string is given?  
>> What does it mean "each instance that references this value"?)
>>
>> It also appears that the text that was added to allow the 
>> seed argument to be a parameter (which is needed if you want 
>> to use $rdist_ to set a parameter, eg the threshold voltage or oxide
>> thickness) may violate P1800's sematics for $random.
>>
>> -Geoffrey
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