RE: [Fwd: Minutes of Verilog-AMS meeting - 31 Jan 2008]

One could, but it was not defined that way. Currently, if you give a
seed argument, it must be a variable.

Shalom 

> Indeed.  However, the syntax shows that the argument to 
> $random may be omitted.  V-AMS explicitly notes that, and 
> says that the simulator will pick a seed -- and, presumably, 
> creates an integer variable to hold the value.
> 
> Thus, one could also allow parameters or integral constants 
> and have the simulator create a variable to hold the value 
> and handle the updates, and just initialize it to the value 
> of the constant expression.
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