There is a schedule problem. It would require permission from the P1800 Working Group. Shalom > -----Original Message----- > From: Sri Chandra [mailto:sri.chandra@FREESCALE.COM] > Sent: Thursday, February 07, 2008 7:40 PM > To: Bresticker, Shalom > Cc: Geoffrey.Coram; Verilog-AMS LRM Committee > Subject: Re: [Fwd: Minutes of Verilog-AMS meeting - 31 Jan 2008] > > Can we impress upon the SV committee to extend the current > syntax? I know it might be a difficult task but thought will > ask rather than assume. > > Regards, > Sri > > Bresticker, Shalom wrote: > > No. > > > >> Is there any plans to include constant seed argument > >> (parameter) to P1800 standards? > > -- > Srikanth Chandrasekaran > Design Technology (Tools Development) > Freescale Semiconductor Inc. > T:+91-120-439 5000 p:x3824 f: x5199 --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Feb 7 19:40:01 2008
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