Re: real-to-integer conversion

Marq,

I agree it should be there just in one place - not sure why it slipped 
out from our earlier document changes. If the solution is just simple 
enough - to remove section 2.6.3 and 3.2.1 then i guess it should be 
simple enough and don't expect any impact to schedule. However, I will 
let Stu comment on this. The plan is to have draft3 that can we start 
reviewing on March 13th, which ideally i don't want to delay.

cheers,
Sri


Marq Kole wrote:
> Hi All,
> 
> It seems that the issue mentioned below is still present in Draft 2 of 
> the 2.3 LRM. Currently the same text on real-to-integer conversion is 
> present in the following sections:
> - section 2.6.3
> - section 3.2.1
> - section 4.2.1.1
> 
> An earlier reply by David Miller suggested to have this text only at 
> section 4.2.1.1 and that all other texts should refer to that section. I 
> have no preference only that it should occur just once and others should 
> refer. Can we include this change in Draft 3?
> 
> Cheers,
> Marq
> 
> 
> owner-verilog-ams@server.eda.org wrote on 16-10-2007 15:21:42:
> 
>  > All,
>  >
>  > And the same text is also present in subsection 4.1.1.1 - do we
>  > really need to hammer this home? :-)
>  >
>  > Cheers,
>  > Marq
>  >
>  > owner-verilog-ams@server.eda.org wrote on 16-10-2007 15:14:14:
>  > > All,
>  > >
>  > > The current Verilog-AMS update proposals for chapter 2 and chapter 3
>  > > contain duplictae information: the first paragraph of section 3.1.1
>  > > is essentially the same as section 2.5.4. Considering that
>  > > conversion is not a lexical convention I would suggest to remove it
>  > > from section 2.5.4 and provide the additional examples of conversion
>  > > in this subsection to section 3.1.1.
>  > >
>  > > Cheers,
>  > > Marq
>  > >
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-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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