Hi Sri, I've checked the email reflector. Clause 3.6.2.1 is OK as per Mantis item 1405, as discussed in an email exchange between Graham Helwig and Ken Kundert from May 1st, 2006. To summarize: the original Verilog-A 1.0 supported both potential-only and flow-only signal flow disciplines. This has been restricted to potential-only signal-flow disciplines in later versions of the standard for unknown reasons. Mantis item 1405 requests to remove the restriction on potential-only signal-flow disciplines and that is what the example in Clause 3.6.2.1 refers to. Essentially, LRM 2.3 Draft 2 has partially implemented this Mantis item. Section 1.3.3 should be updated to support also flow-only signal-flow disciplines. Section 1.3.4 does not contradict this, so no change would be needed there. Section 1.3.4 could be extended with the notion that multiple flow-only sources can be connected together to attach to a single sink, but this explanation may be postponed to a later release if needed. However, another consequence would also be to update the "disciplines.vams" file to reflect this situation, in particular the "current" discipline should be made into a flow-only discipline. I think the latter is an important item. Best regards, Marq owner-verilog-ams@server.eda.org wrote on 31-01-2008 09:07:40: > Marq, > > Is clause 3.6.2.1 in error? For signal-flow disciplines the nature has > to be potential. Current contributions on these nodes are not legal as > the flow nature is not defined for signal-flow systems. There is a > reference made to this in clause 1.3.3 also and the details for > signal-flow is given in clause 1.3.4 > > cheers, > Sri > > Marq Kole wrote: > > Hi All, > > > > The current draft 2 contains an ambiguity: in section 3.6.2.1 on Nature > > Binding an example signal-flow discipline show the current discipline > > with a flow nature, while Annex D.1 shows that in the disciplines.vams > > the current discipline still has a potential nature. In my opinion for > > Verilog-AMS 2.3 the disciplines.vams should be updated to make the > > current discipline have a flow nature. > > > > Currently, in Verilog-AMS 2.2 a module with terminals that have a > > signal-flow nature of current cannot be connected to a net of discipline > > electrical and assume that the current in one connects to the current in > > the other. With the above change this should be resolved. > > > > Cheers, > > Marq > > > > -- > > This message has been scanned for viruses and > > dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is > > believed to be clean. > > > > -- > Srikanth Chandrasekaran > Design Technology (Tools Development) > Freescale Semiconductor Inc. > T:+91-120-439 5000 p:x3824 f: x5199 > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Mar 5 07:47:38 2008
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