Verilog-AMS standardization process

All,

The upcoming 2.3 release for the Verilog-AMS language will be mainly
focused on the integration with the digital Verilog standard IEEE
1364-2005. Next to that there are quite a number of analog-specific items
that got resolved in this text, next to a general clean-up of the document
and the examples. However, there are also a number of mixed signal items
that need to be resolved, for instance, there are some issues on
supply-sensitivity in connect modules for which there is no standardized
solution currently available. The Mantis database for Verilog-AMS issues
has got a number of quite hairy mixed-signal items marked for possible
inclusion in the standard, in general trying to improve the mixed-signal
modelling and simulation possibilities in the language.

Given the current state of affairs none of the abovementioned mixed-signal
items will make it into the 2.3 LRM. On one hand, the above are valid
concerns and could lead to improved usability of Verilog-AMS in particular
in the mixed-signal domain; on the other hand, we do not want to lose the
momentum in the Verilog-AMS LRM 2.3 efforts.

My proposal would be to move ahead with Verilog-AMS 2.3 as fast as
possible, at this time making only the simplest of amendments - preferrably
only those that have come out of the review of draft 2 and items such as
typo's in the LRM 2.2 text. Anything to do with the bigger mixed-signal
items as signaled in Sri's message of February 21 should be postponed. Yet,
in parallel with the final stages of the Verilog-AMS 2.3 LRM I would also
propose to start a mixed-signal subcommittee that would focuses solely on
existing and new items in the mixed-signal part of Verilog-AMS. This would
encompass supply-sensitive connect modules, discipline incompatibility
specification, analog and digital function convergence, analog tasks,
extending wreal to a regular port type with discipline and bidirectional
communication, etc.

The main committee could then consider the merger with SystemVerilog, but
if the subcommittee finishes its work earlier an intermediate release of
the standard may be produced so the mixed-signal developments in the tools
can move ahead and not wait on the additional SystemVerilog integration.
Personally, I would aim for a 1 year timeline, similar to the work in the
compact modeling subcommittee. Of course, whereever SystemVerilog already
offers a solution to any particular mixed-signal items that will be
preferred over any new solutions.

I have already sent a message along the same lines as the text above to a
few of the regular attendees to find out how this proposal would be
received. Actually, all of the responders were quite positive about this.
This has prompted me to ask Sri to add this item to the agenda for
tomorrow's (tonight's) Verilog-AMS standardization conference call.

Best regards,
Marq
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