List of mixed-signal subjects

Hi everyone,

In response to a private question from Shalom for a more specific list of
subjects I have collected the following items as subjects to work on in the
mixed-signal subcommittee.

- Supply sensitivity in connect modules - how to make connect modules
connect to a particular net as a supply reference, and have the connect
modules automatically switch off at low supply. There are a few other
supply net related issues in the Mantis database.
- Discipline compatibility - can mixed-signal designs with multiple supply
domains be made correct by design by declaring disicplines incompatible.
Ken Kundert will make a proposal for this in the LRM 2.3 Draft 3 but this
needs to be extended to wreal at least; it may not even be accepted given
that there has been no open discussion on it.
- Elevate wreal or equivalent SV real to full signal status - use of
Verilog-AMS at a higher abstraction level is currently frustrated by the
limitations on wreal, while communication by means of 64-bit busses for
1364 reals is not an acceptable alternative. Also for this item more issues
are present in Mantis.
- Access to analog variables - how can a safe access to analog variables be
created to make test bench creation simpler and making test bench
structures more powerfull, i.e. revealing more of the (analog) module
internals. This has been discussed in the committee but as no save
resolution was found the LRM 2.3 adopts the position that no such access is
possible. As this is a very interesting and useful feature I would like to
revisit this in the mixed-signal subcommittee.
- convergence of analog and digital functions - call analog fuctions from
digital and vice versa.
- extension of connectrules block - support for local definition of
connectrules so subblocks in an SoC model can be selfcontained.
- stronger integration of analog and digital simulation cycles - make
analog and digital continuously aware of when they will process their next
event/timestep. This can lead to significant efficiency improvements and
prevent hard-to-trace errors in simulation.
- SV assertions in the analog context.
- Support for absolute delay in digital statements.
- Use of SV packages and/or global variables for collecting user-defined
functions and tasks to are to be used in multiple modules.

In addition, I will need to go through the current Mantis items together
with some of the feedback I already received from some users and outside
contacts that I've been talking to.

Best regards,
Marq
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.