Mixed-Signal subcommittee - Call for Participation

Dear All,

As discussed in the Verilog-AMS Standardization Conference Call of Thursday
March 13 we would like to speed things up with respect to the
standardization of Verilog-AMS. The efforts to reach the 2.3 standard are
currently moving towards a final draft in a few weeks time. To keep the
time that will be used for the review process of the intermediate drafts as
short as possible, no new items should be brought into the standard. After
the submission of the final draft, there is also time to be spend in the
acceptance process in the Accellera Technical Board. To support a fast
track towards standardization of LRM 2.3 on one hand and on the other to
address existing and upcoming demands for language extensions in a timely
manner, I propose to organize a mixed-signal subcommittee of the
Verilog-AMS standardization committee.

The main target for the Verilog-AMS standard will be integration with the
IEEE 1800-2005 SystemVerilog standard. If the efforts for converging with
the IEEE 1364-2005 Verilog standard are any sort of measure, this will be a
very substantial effort. The mixed-signal subcommittee is an intermediate
activity to resolve a reasonable set of existing and new feature requests
for (mainly) mixed-signal items in the Verilog-AMS language in a timely
manner. This should improve useability of the language for mixed-signal
applications while users should not have to wait for the finalization of
the SystemVerilog merger to see them in the standard. If the mixed-signal
commitee resolves its issues much earlier than the SystemVerilog
integration efforts, an intermediate version of the Verilog-AMS standard
may result. The efforts to converge with the SystemVerilog standard should
not halt the development of the language standard for other issues and new
developments.

On the practical side, if a mixed-signal item or feature could be addressed
by a SystemVerilog solution, that will be the solution to adopt. The work
of mixed-signal subcommitee shall not interfere with the SystemVerilog
integration efforts. Any solutions will be resolved in line with the
SystemVerilog integration.

The mixed-signal subcommitee would like to start as soon as possible -
target date is the week of April 1st. If you would like to participate in
this subcommittee, you can apply either through the reflector or directly
to me. Based on the response I will set up a conference call to discuss the
organization of the subcommittee and set preliminary targets. I hope to
hear from you soon.

Best regards,

Marq Kole
NXP Semiconductors

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