RE: $finish and final_step

Hi,

it looks to me that:
- final_step blocks may contain way more than just "cleaning" statements
- final_step blocks may be anywhere in the analog block, and as
verilog-AMS has a requirement of executing its statements in sequence,
you can re-execute a block once you have already done the following one.

So the only reasonable way of executing final_step blocks seems to do it
while executing the analog block.
So, if $finish implies final_step, it means:
- the model sends a $finish
- the simulator takes notice and doesn't accept the step
- the simulator reexecutes the step in "final_step" mode

(in real life, it may of course be way more complex because e.g. the
final step won't converge, or it will modify the digital side, etc.).

All this would tend to preferring the solution where $finish just stops
the simu, without final_step. That's fine, but then we have no way of
finishing the simu early *and* calling final_step (which may do some
useful final diagnostics like seen in some examples from the LRM).

	Xav

On Thu, 2008-03-27 at 15:46 +0000, Neugebauer Kurt wrote:
> Hi Dave,
> 
> Exactly, that's how I would like to have it work. 
> 
> Kurt
> 
> -----Original Message-----
> From: Miller Dave 
> Sent: Thursday, March 27, 2008 4:33 PM
> To: Neugebauer Kurt; Martin O'Leary
> Cc: Verilog-AMS LRM Committee
> Subject: Re: $finish and final_step
> 
> Hi Kurt, Martin.
> I am not sure I follow what you mean. $finish should not result in
> another timestep being executed to resolve final_step blocks should it?
> It simply requires that the analog engine performs one iteration on the
> analog instances.
> 
> final_step blocks should (as far as I understand) be executed after the
> simulation has completed and reached a solution. So time is not
> advanced, there is no impact to the circuit solution, etc. final_step is
> simply to clean up file handles, print any strobes etc.
> 
> If $finish is encountered in digital then it would inform analog solver
> that it
>   has completed. Analog would then simply execute final step blocks and
> stop the overall simulation. No need for analog to perform another solve
> or matrix load as it would have temporarily converged before calling
> digital.
> 
> Is this not how it should work?
> 
> Yes LRM2.2 did say that $finish just stops the simulation but during
> reviews I thought we came to the conclusion that stopping an analog/ams
> simulation (via $finish or just normal simulation completion) would
> include execution of final_step blocks.
> 
> Cheers...
> Dave
> 
> 
> Neugebauer Kurt wrote:
> > Hi,
> > 
> > Martin is right, the question is what Design/verification wants here.
> > $finish; in digital is used for end of verification (all tests 
> > complete) or in by event triggered subroutine (i.e. test failure). 
> > There is no need for analog @final_step block to trigger a final 
> > digital event/subroutine, because the digital engine (event triggered)
> 
> > is always in the state wanted.
> > Digital $finish triggering analog final_step: I'm not sure, but do we 
> > need it to i.e. close open output files, do post processing steps in 
> > the analog solver (analog assertions), ... ?
> > 
> > Kurt Neugebauer
> > 
> > 
> > -----Original Message-----
> > From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On 
> > Behalf Of Martin O'Leary
> > Sent: Thursday, March 27, 2008 12:37 AM
> > To: Miller Dave; Xavier Bestel
> > Cc: Verilog-AMS LRM Committee
> > Subject: RE: $finish and final_step
> > 
> > David, Xavier
> > I don't think it is such a straight-forward thing to say. The answer 
> > below seems to only cover $finish executed in an analog block.
> > 
> > In digital, a $finish immediately terminates the simulation. For AMS, 
> > it doesn't make sense to me that we require digital to then execute 
> > the analog solver to do another time step in order to execute the 
> > @final_step blocks after a $finish is encountered when normally a 
> > digital simulators terminate immediately when a $finish occurs.
> > 
> > Also LRM2.2 says that $finish "simply makes the simulator exit" so 
> > this would seem to not be a backwardly compatible change.
> > 
> > Thanks,
> > --Martin
> > 
> > -----Original Message-----
> > From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On 
> > Behalf Of David Miller
> > Sent: Wednesday, March 26, 2008 8:35 AM
> > To: Xavier Bestel
> > Cc: Verilog-AMS LRM Committee
> > Subject: Re: $finish and final_step
> > 
> > Hello Xavier,
> > 
> > yes, $finish should cleanly stop the simulation by converging on this 
> > timestep and executing any final_step blocks.
> > 
> > $stop should converge on the current timestep but not execute 
> > final_step blocks.
> > 
> > Main difference between $finish and $stop is that $stop is more like a
> 
> > pause - the simulation can be resumed. $finish terminates the 
> > simulation.
> > 
> > I am not sure why this is not highlighted in the LRM - I know that we 
> > discuss the simulation control tasks but seems that adding in this 
> > behaviour explicitly was missed. I will make a note to get it added 
> > into next draft of 2.3
> > 
> > 
> > Cheers...
> > Dave
> > 
> > 
> > Xavier Bestel wrote:
> >> Hi,
> >>
> >> should $finish execute the step again with final_step events on ?
> >> I didn't see it specified in the LRM, in a way or in the other.
> >>
> >> Thanks,
> >> 	Xav
> >>
> >>
> > 
> > --
> > =====================================
> > -- David Miller
> > -- Design Technology (Austin)
> > -- Freescale Semiconductor
> > -- Ph : 512 996-7377 Fax: x7755
> > =====================================
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> -- David Miller
> -- Design Technology (Austin)
> -- Freescale Semiconductor
> -- Ph : 512 996-7377 Fax: x7755
> =====================================
> 


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