Re: $finish and final_step

I'm Design Verification.. I want $finish to behave similar to System verilog.. 
run any final and final_steps.. then exit. 

 
Jonathan David
j.david@ieee.org
jb_david@yahoo.com
http://ieee-jbdavid.blogspot.com
Mobile 408 390 2425

----- Original Message ----
From: Neugebauer Kurt <Kurt.Neugebauer@freescale.com>
To: Martin O'Leary <oleary@cadence.com>; Miller Dave <david.l.miller@freescale.com>; Xavier Bestel <Xavier_Bestel@mentor.com>
Cc: Verilog-AMS LRM Committee <verilog-ams@eda.org>
Sent: Thursday, March 27, 2008 1:44:56 AM
Subject: RE: $finish and final_step

Hi,

Martin is right, the question is what Design/verification wants here.
$finish; in digital is used for end of verification (all tests complete)
or in by event triggered subroutine (i.e. test failure). There is no
need for analog @final_step block to trigger a final digital
event/subroutine, because the digital engine (event triggered) is always
in the state wanted.
Digital $finish triggering analog final_step: I'm not sure, but do we
need it to i.e. close open output files, do post processing steps in the
analog solver (analog assertions), ... ?

Kurt Neugebauer 


-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Martin O'Leary
Sent: Thursday, March 27, 2008 12:37 AM
To: Miller Dave; Xavier Bestel
Cc: Verilog-AMS LRM Committee
Subject: RE: $finish and final_step

David, Xavier
I don't think it is such a straight-forward thing to say. The answer
below seems to only cover $finish executed in an analog block.

In digital, a $finish immediately terminates the simulation. For AMS, it
doesn't make sense to me that we require digital to then execute the
analog solver to do another time step in order to execute the
@final_step blocks after a $finish is encountered when normally a
digital simulators terminate immediately when a $finish occurs.

Also LRM2.2 says that $finish "simply makes the simulator exit" so this
would seem to not be a backwardly compatible change.

Thanks,
--Martin 

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of David Miller
Sent: Wednesday, March 26, 2008 8:35 AM
To: Xavier Bestel
Cc: Verilog-AMS LRM Committee
Subject: Re: $finish and final_step

Hello Xavier,

yes, $finish should cleanly stop the simulation by converging on this
timestep and executing any final_step blocks.

$stop should converge on the current timestep but not execute final_step
blocks.

Main difference between $finish and $stop is that $stop is more like a
pause - the simulation can be resumed. $finish terminates the
simulation.

I am not sure why this is not highlighted in the LRM - I know that we
discuss the simulation control tasks but seems that adding in this
behaviour explicitly was missed. I will make a note to get it added into
next draft of 2.3


Cheers...
Dave


Xavier Bestel wrote:
> Hi,
> 
> should $finish execute the step again with final_step events on ?
> I didn't see it specified in the LRM, in a way or in the other.
> 
> Thanks,
>     Xav
> 
> 

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