Old int/logic -> real conversion handling proposal (re 4.2.1.2)

http://www.eda-stds.org/verilog-ams/htmlpages/tc-docs/issues/0013/index.html

I think converting x/z bits to 0 is a recipe for disaster, the old 
proposal was to produce a result of NaN (Not a Number) for the real 
which is handled efficiently by floating point hardware, and only only 
throw an error if NaN gets assigned to a branch. All reals without an 
initial assignment should probably be initialized to NaN rather than zero.

Propose 4.2.1.2 becomes:

    Implicit conversion shall take place when an integer or logic
    expression is assigned to a real. If any bits of the expression are
    x or z then the real value becomes NaN (Not a Number). It is illegal
    to assign NaN to a branch.


- and add NaN as a keyword.

Kev.

-- 
True Circuits Inc. - http://www.truecircuits.com
Tel: (650) 949 3400 Ext 3415


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.