Re: Minutes of the Verilog-AMS call - 27 March 2008

Shalom,

Thanks for clarifying the confusion on apostrophe and curly brackets. 
The assumption was that it will get expanded completely - in fact today 
(v2.2) AMS does not have apostrophe at all, and hence the theory was 
during the meeting the other day that the apostrophe will just go before 
all the opening curly brackets.

I guess we want to be consistent with the SV handles array literals, 
concatenation, apostrophe etc - that is the whole idea of changing the 
current way it is stated in AMS.

cheers,
Sri


Bresticker, Shalom wrote:
> Hi,
> 
> Regarding the following:
>  
>>    - (section 4.2.13, page 59): Confusion between array 
>> literal and concatenation (examples seem to refer to array 
>> literals rather than concat tho' both use the same operator).
> ...
>>      * Leave the last example with replication as is in that section. 
>> There should be a apostrophe - `2`{a,b} in that example.
> 
> Draft 3 does not mention array literals or assignment patterns at all.
> If you want them, you have to describe them in an orderly way.
> 
> (By the way, all apopstrophes in code should be straight up-down simple
> not-smart apostrophes.)
> 
> The mentioned example (again, an example of an array literal or
> assignment pattern, not a concatenation as the text wrongly says) says,
> 
> '{c, '{2{a, b}}} // equivalent to: '{c, a, b, a, b}
> 
> Assuming you want to be compatible with IEEE Std 1800, this is not
> correct.
> 
> '{c, '{2{a, b}}} is equivalent to: '{c, '{a, b, a, b}}
> 
> If you added an apostrophe in the place shown in the minutes, then you
> would get:
> 
> '{c, '{2'{a, b}}} is equivalent to: '{c, '{a, b}, '{a, b}}
> 
> If the original comment following the code is intended, then you need to
> delete the apostrophe before "2":
> 
> '{c, {2{a, b}}} is equivalent to: '{c, a, b, a, b}
> 
> 1800 is very difficult to understand about how the apostrophes and curly
> brackets work in array literals and assignment patterns. Mantis 943 is
> open on that, but it will not be fixed in the next revision of 1800
> unless it is flagged by a ballot voter.
> 
> Regards,
> Shalom
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-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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