RE: Minutes of the Verilog-AMS call - 27 March 2008

Hi,

Regarding the following:
 
>    - (section 4.2.13, page 59): Confusion between array 
> literal and concatenation (examples seem to refer to array 
> literals rather than concat tho' both use the same operator).
...
>      * Leave the last example with replication as is in that section. 
> There should be a apostrophe - `2`{a,b} in that example.

Draft 3 does not mention array literals or assignment patterns at all.
If you want them, you have to describe them in an orderly way.

(By the way, all apopstrophes in code should be straight up-down simple
not-smart apostrophes.)

The mentioned example (again, an example of an array literal or
assignment pattern, not a concatenation as the text wrongly says) says,

'{c, '{2{a, b}}} // equivalent to: '{c, a, b, a, b}

Assuming you want to be compatible with IEEE Std 1800, this is not
correct.

'{c, '{2{a, b}}} is equivalent to: '{c, '{a, b, a, b}}

If you added an apostrophe in the place shown in the minutes, then you
would get:

'{c, '{2'{a, b}}} is equivalent to: '{c, '{a, b}, '{a, b}}

If the original comment following the code is intended, then you need to
delete the apostrophe before "2":

'{c, {2{a, b}}} is equivalent to: '{c, a, b, a, b}

1800 is very difficult to understand about how the apostrophes and curly
brackets work in array literals and assignment patterns. Mantis 943 is
open on that, but it will not be fixed in the next revision of 1800
unless it is flagged by a ballot voter.

Regards,
Shalom
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