Re: Verilog-AMS committee meeting reminder - 3rd April 2008

> I didn't get any feedback on on the connect module placement issue -
> 
>    http://www.verilog.org/mantis/view.php?id=2343
> 
> Does anyone have problems with making the changes?
Hello Kevin,
I am trying to get an understanding of this proposal. Consider a simple module 
setup:

module parent();
   electrical a;
   electrical gnd;
   ground gnd;
   wire net;

   vdc #(.dc(5)) v0(a,gnd);
   mydig d1(a,net);
endmodule

module mydig(in,out);
   wire in; input in;
   wire out; output out;
   assign out = in;
endmodule


Currently the connect module (a2d) to convert the electrical net 'a' to digital 
  'in' is inserted in parent.
Are you proposing that it is inserted in mydig instead?

-- 
=====================================
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
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