David Miller wrote: >> I didn't get any feedback on on the connect module placement issue - >> >> http://www.verilog.org/mantis/view.php?id=2343 >> >> Does anyone have problems with making the changes? > Hello Kevin, > I am trying to get an understanding of this proposal. Consider a > simple module setup: > > module parent(); > electrical a; > electrical gnd; > ground gnd; > wire net; > > vdc #(.dc(5)) v0(a,gnd); > mydig d1(a,net); > endmodule > > module mydig(in,out); > wire in; input in; > wire out; output out; > assign out = in; > endmodule > > > Currently the connect module (a2d) to convert the electrical net 'a' > to digital 'in' is inserted in parent. > Are you proposing that it is inserted in mydig instead? Yes, since the "assign" statement is the actual driving process. Kev. -- True Circuits Inc. - http://www.truecircuits.com Tel: (650) 949 3400 Ext 3415 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Apr 2 14:35:13 2008
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