RE: Verilog-AMS meeting minutes - 17th April 2007

In my opinion, this is not something that should be put into the next LRM
draft at the last minute.  If anything, it much more logically belongs as
part of the AMS subcommittee activities.

I've attempted at least a couple times to understand the logic and reasoning
behind the proposal, but so far I've been totally unsuccessful. 

1) It breaks backward compatibility for no purpose that I can understand.
2) It seems to propose something quite illogical when applied to primitives.
(You can't sensibly move the connect module inside of a primitive module.
Why should you have to do so for other modules?)
3) It seems to have a fundamental underlying philosophy change of connecting
connect modules to drivers and receivers, instead of module ports.  But that
seems fundamentally impossible when it comes to behavioral code.
4) Philosophically, to me, it should be the parent (user/environment) of a
(child) module's usage that establishes the required interfaces.  It
shouldn't be the responsibility of the child to adapt to the parent's
environment.
5) If the issue is access to potential supply nets in the child module that
might not be present in the parent, then there are probably better ways to
address that issue that don't have all the corresponding negative issues.
6) ....

David

 
> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
> Behalf Of Sri Chandra
> Sent: Monday, April 21, 2008 10:11 AM
> To: Kevin Cameron
> Cc: Verilog-AMS LRM Committee
> Subject: Re: Verilog-AMS meeting minutes - 17th April 2007
> 
> Kevin,
> 
> We can discuss this part of the next meeting on May 1st and if its an
> easy fix without much impact for sure we can put it in the next draft. I
> am somehow worried that any fix with connect modules is not an easy fix
> :) Hope you will be able to attend the meeting when this is discussed.
> 
> As with couple of other emails i missed this one also. Sorry about that.
> 
> Regards,
> Sri
> 
> Kevin Cameron wrote:
> >
> > Can we fix the connect module instance placement/naming in the next
> draft?
> >
> > http://www.verilog.org/mantis/view.php?id=2343
> >
> > Kev.
> >
> > Sri Chandra wrote:
> >> Date: 17th April
> >> Attendees:
> >>
> >> Martin O'Leary, Cadence
> >> Marek Mierzwinski, Tiburon
> >> Stu Sutherland, Sutherland-HDL
> >> Marq Kole, NXP
> >> Patrick O'Halloran, Tiburon
> >> Geoffrey Coram, Analog Devices
> >> Sri Chandra, Freescale
> >>
> >>
> >> General:
> >> * Copyrights say 2007, they should be changed to 2008 (ex: page1
> >> footer says Copyright 1999-2007)
> >> * Roman numeral numbering restarts on page 7 of the pdf file
> >> * Change Ken's affiliation to "Designer's Guide Consulting"
> >>
> >> TOC:
> >> * Page iii: Sub-section heading should be "Analog initial block" with
> >> cap A.
> >>
> >> Chapter 3, Data types
> >> * [Syntax 3-2, page 29]: "{}" should be in red in the syntax item
> >> * [clause 3.4.1, page 30]: Reference to sub-clause 3.2.1 is wrong as
> >> this does not exist. This should be changed to 4.2.1.1
> >>
> >> Chapter 4,
> >> * [clause 4.4, page 62]: V(n1,n1) should be added to the table and
> >> recorded as disallowed and return error (rather than allow with return
> >> value of 0) - same as I(n1, n1). I forgot to discuss this in the
> >> meeting yesterday. Marq had sent this email and there was agreement
> >> with no disapproval :) Mantis also raised for the same (2345).
> >> * [clause 4.5.3, page 63]: Not enough row height for the first
> >> description of ddt(expr) in Table 4-17 (as seen in pdf)
> >> * [clause 4.5.4, page 64]: Description of idt(expr) in Table 4-18
> >> should not be italicized
> >> * [clause 4.5.4, page 65]: When BNF is used in paragraph for idt etc
> >> idt() will be used in courier font.
> >> * [clause 4.5.5, page 66]: Description of idtmod(expr) in Table 4-19
> >> should not be italicized
> >>
> >> Chapter 5, Analog behavior
> >> * [clause 5.2, page 89]: "_" missing in syntax 5-1 in "analog initial
> >> analog_function_statement". Same mistake made in A.6.2 on page 345.
> >> * [clause 5.10.3, page 113]: This is applicable for cross/above/timer
> >> sub-sections. The syntax box 5-16, 5-17, 5-18 (and also possibly
> >> syntax 5-13] are missing the enable arguments. This needs to be
> >> updated in BNF also (A.6.5)
> >> * [clause 5.10.3, page 113]: Request for introducing new BNF which
> >> allows user to specify null arguments for certain expressions instead
> >> of adding extra [] to the syntax. It was agreed to create a new token
> >> in the BNF, with slight modification to David's proposal. The square
> >> brackets will be used for these expressions which denote they are
> >> optional.
> >>   - analog_expression_or_null ::= [analog_expression]
> >>   - constant_expression_or_null ::= [analog_expression]
> >>
> >> Chapter 7, Mixed Signal
> >> * [clause 7.2.4, page 150]: Typo on word tolerance (written as
> >> tolerence). Was not discussed but minor typo, approved.
> >> * [clause 7.3.2, page 152]: Reference to var should be changed to
> >> AnalogVar
> >>
> >> Chapter 8, Scheduling semantics
> >> * [clause 8.3.3.2, page 188]: change it's to its (it's wake-up event).
> >> The same mistake occurs in the same paragraph again. This needs to be
> >> checked globally to see where the ' is required.
> >> * [Clause 8.3.3.3, page 190]: For some reason "ddiscrete" comes out as
> >> "ddiscreteo" in the example. Needs to be fixed.
> >>
> >> Chapter 9, System tasks and functions
> >> * [clause 9.13.1, page 220]: Keep $random consistent with 1364. Remove
> >> the non-variable options for the seed argument and remove type_string
> >> also.
> >> [$rdist will still keep their type_string and
> >> integer_parameter_identifier]
> >>
> >> Chapter 10, Compiler directives
> >> * [Clause 10.4, page 248]: Rephrase the last sentence to the following
> >> as per Geoffrey's email.
> >> The `undef compiler directive shall have no effect on predefined
> >> Verilog-AMS macros; the simulator may issue a warning for an attempt
> >> to undefine one of these macros.
> >>
> >> Annex A, BNF
> >> * [clause A.2.5, page 339]: "{}" should be in red for value_range_type
> >> * [clause A.6.2, page 345]: "_" missing in "analog initial
> >> analog_function_statement"
> >> * [clause A.6.5, page 347]: Add BNF for enable argument.
> >> * [clause A.6.11, page 350]: With reference to assert severity_task
> >> since $error, $fatal etc can be used in normal analog blocks it was
> >> decided that the assert syntax references will be removed from the LRM
> >> as its not used.
> >>
> >> Action Items:
> >> * Martin to send proposal on analog random next week.
> >> * I looked at the minutes (March 27th) and Martin was going to send
> >> out the correct text on section 4.2.13 (array literal and
> >> concatenation). Plan is to copy from 1364 for the concatenation
> examples.
> >> * Request to Martin to close the AIs next week for draft4 work.
> >>
> >> General:
> >> * Stu, I remember we decided to put the chapter heading on the top of
> >> the page (as part of the header). I remember discussing it but not
> >> sure what we decided. I just wanted to understand that, and i think it
> >> will be good to have the chapter heading.
> >>
> >> Draft4 date: This was discussed and Stu agreed to target this for
> >> April 30th to be discussed on May 1st.
> >>
> >> Some of the items mentioned in these various emails sent out was
> >> already captured as part of the meeting minutes and hence not detailed
> >> here. Other emails that were sent out is planned to be taken up post
> >> LRM2.3 and depending on the item, will be either taken up by the mixed
> >> signal subcommittee or in the main stream committee for SystemVerilog
> >> AMS integration.
> >>
> >> Next committee Meeting: May 1st 2008.
> >>
> >>
> >> References:
> >> * Emails used for the committee meeting discussions sent to reflector:
> >>   - Email from Geoffrey Coram, 28th March 2008 (Re: Comments on
> >> Version 2.3 draft 3)
> >>   - Email from Xavier Bestel, 28th March 2008 (Re: Comments on Version
> >> 2.3 draft 3)
> >>   - Email from Geoffrey Coram, 28th March 2008 (Re: Comments on
> >> Version 2.3 draft 3): regarding _ missing in the BNF
> >>   - Email from Geoffrey Coram, 28th March 2008 (Re: Comments on
> >> Version 2.3 draft 3): Starts with comments from Page 152 (169 of PDF)
> >>   - Email from Geoffrey Coram, 28th March 2008 (Re: Comments on
> >> Version 2.3 draft 3): talks about `define and `undef
> >>   - Mantis on V(n1,n1): http://www.verilog.org/mantis/view.php?id=2345
> >>   - Email from Ken Kundert, 28th March 2008 (Comments on Version 2.3
> >> draft 3)
> >>   - enable argument missing in BNF for cross - email from Dave miller
> >> on 3rd April
> >>
> >> * Reference to minutes on the two previous reviews
> >>   - Minutes of meeting on March 27th
> >>   - Subject: "Minutes of the Verilog-AMS call - 27 March 2008", sent
> >> on 31st March 2008 by Sri
> >>   - Subject: "Minutes Verilog-AMS committee meeting - 3rd April 2008",
> >> sent on 4th April by Marq
> >>
> >> cheers,
> >> Sri
> >
> >
> 
> --
> Srikanth Chandrasekaran
> Design Technology (Tools Development)
> Freescale Semiconductor Inc.
> T:+91-120-439 5000 p:x3824 f: x5199
> 
> --
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