RE: Verilog-AMS Committee Meeting - 12 May 2008 (Monday)

In has been suggested in e-mails that I add the semicolon to all discipline
examples.  It is not clear to me from your wording in this message if this
to be an exception, and purposely not have a semicolon.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898

> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
> Behalf Of Geoffrey.Coram
> Sent: Monday, May 12, 2008 9:02 AM
> To: Sri Chandra
> Cc: 'Verilog-AMS LRM Committee'; stuart@sutherland-hdl.com
> Subject: Re: Verilog-AMS Committee Meeting - 12 May 2008 (Monday)
> 
> Here's an example taken from the mixed-signal chapter.
> Note that I've left off the ";" from the discipline
> declaration -- also, I've fixed the AnalogVar -> avar
> problems that were still present on page 152 (166 of 407)
> of Draft4-preliminary
> 
> 
> `begin_keywords "VAMS-2.3"
> discipline logic
>    domain discrete
> enddiscipline
> module a2d(dnet, anet);
>    input dnet;
>    wire dnet;
>    logic dnet;
>    output anet;
>    electrical anet;
>    real avar;
>    analog begin
>      if (dnet === 1'b1)
>        avar = 5;
>      else if (dnet === 1'bx)
>        avar = avar; // hold value
>      else if (dnet === 1'b0)
>        avar = 0;
>      else if (dnet === 1'bz)
>        avar = 2.5; // high impedance - float value
>      V(anet) <+ avar;
>    end
> endmodule
> `end_keywords
> 
> 
> 
> Geoffrey.Coram wrote:
> >
> > Page 243 (257 of 407):
> > Can we add an example that uses a 1800 keyword and VAMS-2.3?
> > Eg "logic" ?
> >
> >
> >
> > Lastly: can we get an index?
> >
> >
> > -Geoffrey
> >
> 
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